Integrated circuit devices, such as high speed semiconductor memory devices, typically input and output data in-synch with an externally applied clock signal. For example, in a high speed semiconductor memory device, data input and output operations may utilize an internal clock signal. In general, in order to improve the performance of a computer system or other device utilizing such memory devices, it is necessary to increase the operating speed of a central processing unit (CPU) and the operation speed of a memory device for storing data and programs requested by the CPU (for example by increasing the speed of the applied clock signal). Recently, in order to improve the operating speed of memory devices to support higher clock rates, a fast page mode dynamic random access memory (DRAM), an extended data output (EDO) DRAM, a synchronous DRAM, a double data rate (DDR) DRAM, and a rambus DRAM have been developed. The operating speed of the memory device is generally increased under various conditions with each of the above DRAMs by increasing the amount of input and output data (bandwidth) accessed per unit time.
However, in the case of some high speed memory devices, such as the rambus DRAM, in which an address latch signal and a column control signal are input at different points in time, the operating speed of the memory device may be limited due to a delay in data access time (hereinafter referred to as t.sub.DAC) between the point in time at which the column control signal is received to the point in time at which a data signal (RD) is output by the memory device.
The delay time in memory access will now be further described with referrence to FIG. 1. FIG. 1 is a timing diagram illustrating various signals on such a memory device which illustrates the factors which may impact the t.sub.DAC in such a conventional memory device. As shown in FIG. 1, the memory device synchronizes memory access operations with reference to a system clock signal CLK, a column latch signal COLLAT and an input/output data command signal COLCYC (hereinafter referred to as a data command signal). One memory read access cycle is shown in FIG. 1. An address input Ai designating the desired memory location for an input or output operation is received by the memory device and synchronized with the system clock signal CLK. The address input Ai is used to generate a column address CAi in response to the column latch signal COLLAT.
A master clock signal COLMASTER is generated in response to the data command signal COLCYC. A decoded column address DCAij is generated from the address input Ai responsive to the master clock signal COLMASTER. Furthermore, a column selection signal CSL for driving a column selection line corresponding to the decoded column address DCAij is activated also in response to the master clock signal COLMASTER.
When the column selection signal CSL is activated (which for the illustrated embodiment is illustrated as the high level), data amplified by a bit line sense amplifier is loaded onto a pair of local input and output lines IO and IOB. As understood by those of skill in the art and figuratively illustrated in FIG. 1 on the IO, IOB line by the ramped signal transition, a differential voltage signal is generated over a period of time between the input and output line IO and the complementary input and output line IOB after the data amplified by the bit line sense amplifier is loaded.
Also shown in FIG. 1, an input and output sense amplifier enable signal PIOSE is enabled or activated (shown in FIG. 1 as a high level) responsive to data command signal COLCYC. The output sense amplifier enable signal PIOSE is used to enable an output sense amplifier which outputs the data signal RD. As shown in FIG. 1, the timing of enable events for the conventional device illustrated is arranged by the use of the COLLAT and COLCYC signals so that the output sense amplifier is not enabled by the PIOSE signal until a point in time at which the voltage difference .DELTA.VIO is no less than a specified value. In other words, PIOSE is not enabled until an appropriate delay time after the pair of local input and output lines IO and IOB have been loaded.
As shown in FIG. 1, the time delay of interest, t.sub.DAC, is the time from the point in time at which the data command signal COLCYC (also corresponding to the column control signal) is activated, to the point in time at which the data signal RD is output. The t.sub.DAC is a recognized parameter for establishing the operating speed, and, particularly, the read speed, of the memory device.
The duration of t.sub.DAC may be unacceptable for certain applications because the column selection signal CSL is itself activated (high level in FIG. 1) responsive to the data command signal COLCYC. The data signal RD should only be output after the data signal of the pair of local input and output lines IO and IOB is developed and a certain voltage difference .DELTA.VIO is generated between the pair of input and output lines IO and IOB. However, as the master clock signal COLMASTER is first generated to decode columns and the column selection line is activated in order to develop the data signal in the pair of local input and output lines IO and IOB, both operations involving a certain time to complete, the operating speed of the memory device may be limited by the sequence of events in reliably generating the data signal in the pair of local input and output lines IO and IOB for output as the data signal RD. In other words, based on the operations sequence as shown in the prior art approach of FIG. 1, the respective use of the column selection signal CSL and the data command signal COLCYC may reduce the data read speed.